R8CSLASH15 datasheet(266/277 Pages) RENESAS

266 / 277 page

C - 1

REVISION HISTORY

R8C/14 Group, R8C/15 Group Hardware

Rev.

Date

Description

Page

Summary

0.10

May 17, 2004

−

First Edition issued

0.20

Jul 12, 2004

−

Rev.0.20 issued

0.30

Aug 06, 2004

all pages

14,15

20-25

26-35

80-84

100

105

107

Words standardized (on-chip oscillator, serial interface, SSU)

Table 1.1 revised

Table 1.2 revised

Table 1.5 revised

Table 1.6 added

“Address Break” in Figures 3.1 and 3.2 ; notes added

Table 4.1, HRA2 Register at 0022h added ; NOTE2 to 6 revised

Table 4.3 the value after reset to FFh at 009Ch to 009Fh revised

Tabel 4.4, the value after reset to FFh at 009Ch to 009Fh revised ;

NOTES added

Compositions and contents of “5. Reset” modified

Compositions and contents of “6. Voltage Detection Circuit” modified

Figure 7.2, function of b0 revised

Figure 9.1 revised

Figure 9.2, “System” at CM06 bit added

Figure 9.3, “System” at CM16 and CM17 bits added

Figure 9.5 revised

9.2.2, “The oscillation starts...HRA2 registers” added

9.3.1 added

9.3.3 “The clock...divided-by-i”added

Table 9.4 revised

11.1.3.4, “Address Break Interrup” added ; the referred distination to “20.

On-Chip Debugger” revised

Table 11.1, some referred distinations revised

Table 11.2, some referred distinations revised

Figures 11.7 and 11.8 added

11.2.1, “The INT0 pin...timer Z” added

11.2.3, “The INT0 pin...CNTR01 pin” added

11.2.4, “The INT3 pin is used with the TCIN pin” added

Compositions and contents of “12. Watchdog Timer” modified

Figure 13.2 revised

Table 13.2 revised

Table 13.3 revised

Figure 13.5 revised

Table 13.4 revised

Figure 13.6 revised

Table 13.5 revised

Figure 13.7 revised

Table 13.6 revised

Figure 13.9 revised

Figure 13.10 revised

13.2 revised

Table 13.7 revised

Table 13.8 revised

REVISION HISTORY

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