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R8C/15 Folha de dados(PDF) 75 Page - Renesas Technology Corp

Nome de Peças R8C/15
Descrição Electrónicos  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
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R8C/14 Group, R8C/15 Group
11. Interrupt
Rev.2.10
Jan 19, 2006
Page 63 of 253
REJ09B0164-0210
11.1.6.1
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
11.1.6.2
IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the
IR bit is set to “0” (= interrupt not requested).
The IR bit can be set to “0” by a program. Do not write “1” to this bit.
11.1.6.3
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority
Levels Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one
another.
Table 11.3
Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits
Interrupt Priority Level
Priority Order
000b
Level 0 (interrupt disabled)
−
001b
Level 1
Low
010b
Level 2
011b
Level 3
100b
Level 4
101b
Level 5
110b
Level 6
111b
Level 7
High
Table 11.4
Interrupt Priority Levels Enabled by
IPL
IPL
Enabled Interrupt Priority Levels
000b
Interrupt level 1 and above
001b
Interrupt level 2 and above
010b
Interrupt level 3 and above
011b
Interrupt level 4 and above
100b
Interrupt level 5 and above
101b
Interrupt level 6 and above
110b
Interrupt level 7 and above
111b
All maskable interrupts are disabled



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