R8CSLASH15 datasheet(179/277 Pages) RENESAS

Nome de Peças	R8C/15

Descrição Electrónicos	16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C/Tiny SERIES

PDF	277 Pages

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179 / 277 page

R8C/14 Group, R8C/15 Group

15. Clock Synchronous Serial I/O with Chip Select (SSU)

Rev.2.10

Jan 19, 2006

Page 167 of 253

REJ09B0164-0210

15.6.4

SCS Pin Control and Arbitration

When setting the SSUMS bit in the SSMR2 register to “1” (4-wire bus communication mode).and the

CSS1 bit in the SSMR2 register to “1” (functions as SCS output pin), Set the MSS bit in the SSCRH

serial transfer. If the SSU detects that the synchronized internal SCS signal is held “L” in this period,

the CE bit in the SSSR register to “1” (a conflict error occurs) and the MSS bit is automatically set to

“0” (operates as a slave device).

Figure 15.20 shows an Arbitration Check Timing.

A future transmit operation is not performed while the CE bit is set to “1”. Set the CE bit to “0” (a

conflict error does not occur) before a transmit is started.

Figure 15.20

Arbitration Check Timing

Data Write to

SSTDR Register

Maximum Time of SCS Internal

Synchronization

During Arbitration Detection

High-Impedance

SCS Input

Internal SCS

(Synchronization)

MSS Bit in

SSCRH Register

Transfer Start

SCS Output

“0”

“1”

R8C/15 Folha de dados(PDF) 179 Page - Renesas Technology Corp