H8SLASH3024 datasheet(77/841 Pages) RENESAS

Nome de Peças	H8/3024

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 39 of 800

REJ09B0260-0200

Table 2.9

System Control Instructions

Instruction Size*

Function

TRAPA

—

Starts trap-instruction exception handling

RTE

—

Returns from an exception-handling routine

SLEEP

—

Causes a transition to the power-down state

LDC

B/W

(EAs)

→ CCR

Moves the source operand contents to the condition code register. The

condition code register size is one byte, but in transfer from memory, data is

read by word access.

STC

B/W

CCR

→ (EAd)

Transfers the CCR contents to a destination location. The condition code

access.

ANDC

CCR

∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC

CCR

∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC

CCR

⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP

—

PC + 2

→ PC

Only increments the program counter.

Note: * Size refers to the operand size.

B: Byte

W: Word

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