H8SXSLASH1663M datasheet(156/1504 Pages) RENESAS

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Section 6 Exception Handling

Rev. 2.00 Sep. 24, 2008 Page 124 of 1468

REJ09B0412-0200

The interrupt exception handling is as follows:

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the interrupt source is generated,

the start address of the exception service routine is loaded from the vector table to PC, and

program execution starts from that address.

6.7

Instruction Exception Handling

There are three instructions that cause exception handling: trap instruction, sleep instruction, and

illegal instruction.

6.7.1

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state. The trap

instruction exception handling is as follows:

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the vector number specified in

the TRAPA instruction is generated, the start address of the exception service routine is loaded

from the vector table to PC, and program execution starts from that address.

A start address is read from the vector table corresponding to a vector number from 0 to 3, as

specified in the instruction code.

Table 6.8 shows the state of CCR and EXR after execution of trap instruction exception handling.

Table 6.8

Status of CCR and EXR after Trap Instruction Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0



[Legend]

Set to 1

Cleared to 0

:

Retains the previous value.

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