H8SXSLASH1663M datasheet(68/1504 Pages) RENESAS

Nome de Peças	H8SX/1663M

Descrição Electrónicos	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 36 of 1468

REJ09B0412-0200

• Exception Vector Table and Memory Indirect Branch Addresses

In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One

branch address is stored per 16 bits. The structure of the exception vector table is shown in

figure 2.2.

H'0000

H'0001

H'0002

H'0003

Reset exception vector

Exception

vector table

Figure 2.2 Exception Vector Table (Normal Mode)

The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes

are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction

code specifies a memory location. Execution branches to the contents of the memory location.

• Stack Structure

The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.

(a) Subroutine Branch

(b) Exception Handling

(16 bits)

EXR*1

Reserved*1, *3

CCR

CCR*3

(16 bits)

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP*2

)

Figure 2.3 Stack Structure (Normal Mode)

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