H8SXSLASH1663M datasheet(1090/1504 Pages) RENESAS

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Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1058 of 1468

REJ09B0412-0200

21.4.5

Slave Receive Operation

In slave receive mode, the master device outputs the transmit clock and the transmit data, and the

slave device returns an acknowledge signal. Figures 21.11 and 21.12 show the operation timings

in slave receive mode. The reception procedure and operations in slave receive mode are described

below.

1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the

WAIT bit in ICMR or CKS3 to CKS0 in ICCRA (initial setting). Set the MST and TRS bits in

ICCRA to select slave receive mode and wait until the slave address matches.

2. When the slave address matches in the first frame following detection of the start condition,

the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the

ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read).

(Since the read data shows the slave address and R/

W, it is not used).

3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is

fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting

before reading ICDRR to be returned to the master device is reflected in the next transmit

frame.

4. The last byte data is read by reading ICDRR.

SDA

(Master output)

SCL

(Slave output)

SDA

(Slave output)

ICDRS

ICDRR

SCL

(Master output)

Data 2

Data 1

RDRF

Data 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

User

processing

[2] Read ICDRR (dummy read)

[2] Read ICDRR

Figure 21.11 Slave Receive Mode Operation Timing 1

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