H8SXSLASH1663M datasheet(867/1504 Pages) RENESAS

Nome de Peças	H8SX/1663M

Descrição Electrónicos	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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867 / 1504 page

Section 16 8-Bit Timers (TMR)

Rev. 2.00 Sep. 24, 2008 Page 835 of 1468

REJ09B0412-0200

16.5.4

Timing of Counter Clear by Compare Match

TCNT is cleared when compare match A or B occurs, depending on the settings of the bits

CCLR1 and CCLR0 in TCR. Figure 16.11 shows the timing of this operation.

H'00

Compare match

signal

TCNT

Figure 16.11 Timing of Counter Clear by Compare Match

16.5.5

Timing of TCNT External Reset*

TCNT is cleared at the rising edge or high level of an external reset input, depending on the

settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure

16.12 and Figure 16.13 shows the timing of this operation.

Note: * Clearing by an external reset is available only in units 0 and 1.

Clear signal

External reset

input pin

TCNT

H'00

N – 1

Figure 16.12 Timing of Clearance by External Reset (Rising Edge)

Clear signal

External reset

input pin

TCNT

H'00

N – 1

Figure 16.13 Timing of Clearance by External Reset (High Level)

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