H8SXSLASH1663M datasheet(799/1504 Pages) RENESAS

Nome de Peças	H8SX/1663M

Descrição Electrónicos	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 767 of 1468

REJ09B0412-0200

14.10

Usage Notes

14.10.1

Module Stop Function Setting

Operation of the TPU can be disabled or enabled using the module stop control register. The initial

setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop

state. For details, see section 28, Power-Down Modes.

14.10.2

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 14.46 shows the input clock

conditions in phase counting mode.

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Overlap

Phase

difference

Pulse width

Note: Phase difference, Overlap

≥ 1.5 states

Pulse width

≥ 2.5 states

Pulse width

Phase

difference

Overlap

Pulse width

Figure 14.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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