H8SXSLASH1663M datasheet(593/1504 Pages) RENESAS

Nome de Peças	H8SX/1663M

Descrição Electrónicos	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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593 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 561 of 1468

REJ09B0412-0200

12.2

DTC has the following registers.

• DTC mode register A (MRA)

• DTC mode register B (MRB)

• DTC source address register (SAR)

• DTC destination address register (DAR)

• DTC transfer count register A (CRA)

• DTC transfer count register B (CRB)

These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the

CPU. The contents of these registers are stored in the data area as transfer information. When a

DTC activation request occurs, the DTC reads a start address of transfer information that is stored

in the data area according to the vector address, reads the transfer information, and transfers data.

After the data transfer, it writes a set of updated transfer information back to the data area.

• DTC enable registers A to F (DTCERA to DTCERF)

• DTC control register (DTCCR)

• DTC vector base register (DTCVBR)

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