H8SXSLASH1663M datasheet(525/1504 Pages) RENESAS

525 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 493 of 1468

REJ09B0412-0200

The source address extended repeat area is specified by bits SARA4 to SARA0 in EDACR, and

the destination address extended repeat area by bits DARA4 to DARA0 in EDACR. The size of

each extended repeat area can be specified independently.

When the address register value is the last address in the extended repeat area and extended repeat

area overflow occurs, EXDMA transfer can be temporarily halted and an extended repeat area

overflow interrupt request can be generated for the CPU. If the SARIE bit in EDACR is set to 1,

and the EDSAR extended repeat area overflows, the ESIF bit is set to 1 and the DTE bit cleared to

0 in EDMDR, and transfer is terminated. If the ESIE bit is set to 1 in EDMDR, an extended repeat

area overflow interrupt is requested to the CPU. If the DARIE bit in EDACR is set to 1, the above

applies to the destination address register. If the DTE bit in EDMDR is set to 1 during interrupt

generation, transfer is resumed.

Figure 11.15 illustrates the operation of the extended repeat area function.

External memory

When lower 3 bits (8-byte area) of EDSAR are designated

as extended repeat area (SARA4 to SARA0 = B'00011)

Repeat

Extended repeat area overflow

interrupt can be requested

Range of

EDSAR values

H'23FFFE

H'23FFFF

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

H'240008

H'240009

H'240000

H'240001

H'240002

H'240003

H'240004

H'240005

H'240006

H'240007

Figure 11.15 Example of Extended Repeat Area Function Operation

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