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H8SX/1663M Folha de dados(PDF) 337 Page - Renesas Technology Corp

Nome de Peças H8SX/1663M
Descrição Electrónicos  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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H8SX/1663M Folha de dados(HTML) 337 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 305 of 1468
REJ09B0412-0200
(2)
When DDS = 0 or EDDS = 0
Single address transfer by the DMAC or EXDMAC takes place as a full access (normal access).
The
DACK and EDACK signals are asserted within the Tr cycle and the BS signal is also asserted
during the Tr cycle.
When the DRAM space is accessed with other than the single address transfer by the DMAC or
EXDMAC, a fast-page access is available.
Figure 9.59 shows an output timing example of the
DACK and EDACK signals when DDS = 0 or
EDDS = 0.
DACK or
EDACK
DKC, EDKC = 1
DKC, EDKC = 0
T
p
T
r
T
c1
T
c2
T
c3
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
BS
RD/
WR
Figure 9.59 Output Timing Example of
DACK and EDACK when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)



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