H8SLASH3008 datasheet(77/686 Pages) RENESAS

Nome de Peças	H8/3008

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

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2. CPU

Rev.4.00 Aug. 20, 2007 Page 33 of 638

REJ09B0395-0400

Table 2.5

Logic Operation Instructions

Instruction Size*

Function

AND

B/W/L

∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general

B/W/L

∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general

XOR

B/W/L

⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another

general register or immediate data.

NOT

B/W/L

¬ Rd → Rd

Takes the one's complement (logical complement) of general register

contents.

Note:

Size refers to the operand size.

Byte

W: Word

Longword

Table 2.6

Shift Instructions

Instruction Size*

Function

SHAL,

SHAR

B/W/L

Rd (shift)

→ Rd

Performs an arithmetic shift on general register contents.

SHLL,

SHLR

B/W/L

Rd (shift)

→ Rd

Performs a logical shift on general register contents.

ROTL,

ROTR

B/W/L

Rd (rotate)

→ Rd

Rotates general register contents.

ROTXL,

ROTXR

B/W/L

Rd (rotate)

→ Rd

Rotates general register contents, including the carry bit.

Note:

Size refers to the operand size.

Byte

W: Word

Longword

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