HD6417618A datasheet(293/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 261 of 610

REJ09B0131-0600

12.2.1

E-DMAC Mode Register (EDMR)

EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC.

The settings in this register are normally made in the initialization process following a reset. If the

EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal

data may be sent onto the line. Operating mode settings must not be changed while the transmit

and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC

modules are got into at their initial state by means of the software reset bit (SWR) in this register,

then make new settings. It takes 64 cycles of the internal bus clock B

φ to initialize the EtherC and

E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of

the internal bus clock B

φ has elapsed.

Bit

Bit Name

Initial

value

R/W

Description

31 to 7



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

E-DMAC Data Endian Convert

Selects whether or not the endian format is converted

on data transfer by the E-DMAC. However, the

endian format of the descriptors and E-DMAC register

values are not converted regardless of this bit setting.

0: Endian format not converted (big endian)

1: Endian format converted (little endian)

DL1

DL0

R/W

Descriptor Length

These bits specify the descriptor length.

00: 16 bytes

01: 32 bytes

10: 64 bytes

11: Reserved (setting prohibited)

3 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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