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HD6417618A Folha de dados(PDF) 63 Page - Renesas Technology Corp

Nome de Peças HD6417618A
Descrição Electrónicos  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
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HD6417618A Folha de dados(HTML) 63 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 6.00 Jun. 12, 2007 Page 31 of 610
REJ09B0131-0600
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
PC relative
Rn
Effective address is sum of PC and Rn.
PC
PC
+ Rn
Rn
+
PC + Rn
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction
is zero-extended and multiplied by 4.
2.4.3
Instruction Formats
This section describes the instruction formats, and the meaning of the source and destination
operands. The meaning of the operands depends on the instruction code. The following symbols
are used in the table.
xxxx:
Instruction code
mmmm:
Source register
nnnn:
Destination register
iiii:
Immediate data
dddd:
Displacement



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