HD6417618A datasheet(182/646 Pages) RENESAS

Nome de Peças	HD6417618A

Descrição Electrónicos	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 150 of 610

REJ09B0131-0600

7.5.3

Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to

WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in

read access and in write access. The areas other than 4, 5A, and 5B have the same access wait for

read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a

normal space access shown in figure 7.9.

CKIO

A25 to A0

CSn

RD/

D15 to D0

WEn(BEn)

Read

Write

Figure 7.8 Wait Timing for Normal Space Access (Software Wait Only)

When the WM bit in CSnWCR is cleared to 0, the external wait signal (

WAIT) is also sampled.

The

WAIT pin sampling is shown in figure 7.9. In this example, two wait cycles are inserted as

software wait. The

WAIT signal is sampled at the falling edge of the CKIO signal in the cycle

immediately before the T2 cycle (T1 or Tw cycle).

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