HD6417618A datasheet(160/646 Pages) RENESAS

Nome de Peças	HD6417618A

Descrição Electrónicos	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 128 of 610

REJ09B0131-0600

• CS6BWCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BAS

R/W

Byte Access Selection for Byte-Selection SRAM

Specifies the

WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the

WEn (BEn) signal at the read/write timing

(signal used as strobe) and asserts the RD/

WR signal

during the write access cycle (signal used as status)

1: Asserts the

WEn (BEn) signal during the read/write

access cycle (used as status) and asserts the RD/

signal at the write timing (used as strobe)

19 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SW1

SW0

R/W

Number of Delay Cycles from Address,

CSn Assertion to

RD, WEn (BEn) Assertion

Specify the number of delay cycles from address and

CSn assertion to RD and WEn (BEn) assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

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