HD6417618A datasheet(446/646 Pages) RENESAS

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Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 414 of 610

REJ09B0131-0600

When the external DMAC is specified to detect high level of the HIFDREQ signal, set DMD = 0

and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after writing 1

to the DTRG bit, HIFDREQ remains high until low level is detected for both the

HIFCS and

HIFRS signals.

In this case, when the HIFDREQ signal is used, make sure that the setup time (

HIFCS assertion to

HIFRS settling) and the hold time (HIFRS hold to

HIFCS negate) are satisfied. If t

HIFAS and tHIFAH

stipulated in section 21.4.9, HIF Timing, are not satisfied, the HIFDREQ signal may be negated

unintentionally.

DTRG bit

DPOL bit

HIFDREQ

HIFCS

HIFRS

Negated in synchronization

with the DPOL bit being set

by the on-chip CPU.

The DTRG bit is cleared

simultaneously with

HIFDREQ negate.

Negated when

HIFCS = HIFRS = low level.

Latency is tPCYC (peripheral clock cycle)

× 3 cyc or less.

Asserted in synchronization

with the DTRG bit being set

by the on-chip CPU.

Figure 15.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)

When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD

= 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is

generated at the HIFDREQ pin.

DTRG bit

DPOL bit

HIFDREQ

After assert, negated when

tPCYC (peripheral clock cycle)

× 32 cyc have elapsed.

Asserted in synchronization

with the DTRG bit being set

by the on-chip CPU.

The DTRG bit is cleared

simultaneously with

HIFDREQ negate.

Figure 15.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)

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