HD6417618 datasheet(634/646 Pages) RENESAS

634 / 646 page

Rev. 6.00 Jun. 12, 2007 Page 602 of 610

REJ09B0131-0600

Item

Page Revision (See Manual for Details)

Figure 21.16 Synchronous

DRAM Single Read Bus Cycle

(Auto-Precharge,

CAS Latency = 2, WTRCD = 0

Cycle, WTRP = 0 Cycle)

559

Amended

Tc1

Tcw

Td1

Tde

tAD1

CKIO

A25 to A0

Row address

Column address

Figure 21.17 Synchronous

DRAM Single Read Bus Cycle

(Auto-Precharge,

CAS Latency = 2, WTRCD = 1

Cycle, WTRP = 1 Cycle)

560

Amended

Trw

Tc1

Tcw

Td1

Tde

Tap

tAD1

CKIO

A25 to A0

Row address

Column address

Figure 21.18 Synchronous

DRAM Burst Read Bus Cycle

(Single Read

× 4)

(Auto-Precharge, CAS Latency =

2, WTRCD = 0 Cycle, WTRP = 1

Cycle)

561

Amended

TC1

TC2

Td1

Td2

Td3

Td4

Tc4

Tde

tAD1

CKIO

A25 to A0

Row

address

Column

address

Column

address

Column

address

Column

address

Figure 21.19 Synchronous

DRAM Burst Read Bus Cycle

(Single Read

× 4)

(Auto-Precharge, CAS Latency =

2, WTRCD = 1 Cycle, WTRP = 0

Cycle)

562

Amended

Tc1

Tc2

Td1

Td2

Td3

Td4

Trw

Tc3

Tc4

Tde

tAD1

CKIO

A25 to A0

Row

address

Column

address

Column

address

Column

address

Column

address

Figure 21.20 Synchronous

DRAM Single Write Bus Cycle

(Auto-Precharge, TRWL = 1

Cycle)

563

Amended

Trwl

Tc1

tAD1

CKIO

A25 to A0

Row address

Column address

Figure 21.21 Synchronous

DRAM Single Write Bus Cycle

(Auto-Precharge, WTRCD = 2

Cycles, TRWL = 1 Cycle)

564

Amended

Trw

Tc1

Trwl

Trw

tAD1

CKIO

A25 to A0

Row address

Column address

Figure 21.22 Synchronous

DRAM Burst Write Bus Cycle

(Single Write

× 4)

(Auto-Precharge, WTRCD = 0

Cycle, TRWL = 1 Cycle)

565

Amended

Tc2

Tc3

Tc4

Trwl

Tc1

tAD1

CKIO

A25 to A0

Row

address

Column

address

Column

address

Column

address

Column

address

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