HD6417618 datasheet(413/646 Pages) RENESAS

Nome de Peças	HD6417618

Descrição Electrónicos	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 381 of 610

REJ09B0131-0600

In receiving, the SCIF operates as follows:

1. The SCIF synchronizes with serial clock input or output and initializes internally.

2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the

data, the SCIF checks the receive data can be loaded from SCRSR into SCFRDR or not. If this

check is passed, the SCIF stores the received data in SCFRDR. If the check is not passed

(overrun error is detected), further reception is prevented.

3. After setting RDF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCSCR,

the SCIF requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE

bit or REIE bit in SCSCR is also set to 1, the SCIF requests a break interrupt (BRI).

Figure 14.17 shows an example of SCIF receive operation.

Synchronization

clock

Serial data

RDF

ORER

Data read from

SCFRDR and

RDF flag cleared

to 0 by RXI

interrupt handler

One frame

Bit 7

LSB

RXI

interrupt

request

MSB

Bit 0

Bit 6

Bit 7

Bit 0

Bit 1

BRI interrupt request

by overrun error

RXI

interrupt

request

Figure 14.17 Example of SCIF Receive Operation

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