7477 datasheet(13/48 Pages) RENESAS

13 / 48 page

MITSUBISHI MICROCOMPUTERS

7477/ 7478 GROUP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

When the device is put into power-down state by the STP instruc-

tion or the WIT instruction, if bit 5 in the edge polarity selection

rupt. When a key on wake up interrupt is valid, an interrupt request

is generated by applying the “L” level to any pin in port P0. In this

case , the port used for interrupt must have been set for the input

mode.

If bit 5 in the edge polarity selection register is “0” when the device

is in power-down state, the INT1 interrupt is selected. Also, if bit 5

in the edge polarity selection register is set to “1” when the device

is not in a power-down state, neither key on wake up interrupt re-

quest nor INT1 interrupt request is generated.

The CNTR0/CNTR1 interrupts function in the same as INT0 and

INT1. The interrupt input pin can be specified for either CNTR0 or

CNTR1 pin by setting bit 4 in the edge polarity selection register.

Figure 4 shows the structure of the edge polarity selection regis-

ter, interrupt request registers 1 and 2, and interrupt control

registers 1 and 2.

Interrupts other than the BRK instruction interrupt and reset are

accepted when the interrupt enable bit is “1”, interrupt request bit

is “1”, and the interrupt disable flag is “0”. The interrupt request bit

can be reset with a program, but not set. The interrupt enable bit

can be set and reset with a program.

Reset is treated as a non-maskable interrupt with the highest pri-

ority. Figure 5 shows interrupts control.

Interrupt source

______

RESET

INT0 interrupt

INT1 interrupt or key on wake up interrupt

CNTR0 interrupt or CNTR1 interrupt

Timer 1 interrupt

Timer 2 interrupt

Timer 3 interrupt

Timer 4 interrupt

Serial I/O receive interrupt

Serial I/O transmit interrupt

A-D conversion completion interrupt

BRK instruction interrupt

Priority

Vector addresses

FFFF16, FFFE16

FFFD16, FFFC16

FFFB16, FFFA16

FFF916, FFF816

FFF716, FFF616

FFF516, FFF416

FFF316, FFF216

FFF116, FFF016

FFEF16, FFEE16

FFED16, FFEC16

FFEB16, FFEA16

FFE916, FFE816

Remarks

Non-maskable

External interrupt (polarity programmable)

External interrupt (INT1 is polarity programmable)

External interrupt (polarity programmable)

Non-maskable software interrupt

Table 1. Interrupt vector address and priority.

INTERRUPTS

Interrupts can be caused by 13 different sources consisting of five

external, seven internal, and one software sources.

Interrupts are vectored interrupts with priorities shown in Table 1.

Reset is also included in the table because its operation is similar

to an interrupt.

When an interrupt is accepted, the registers are pushed, interrupt

disable flag I is set, and the program jumps to the address speci-

fied in the vector table. The interrupt request bit is cleared

automatically. The reset and BRK instruction interrupt can never

be disabled. Other interrupts are disabled when the interrupt dis-

able flag is set.

All interrupts except the BRK instruction interrupt have an interrupt

request bit and an interrupt enable bit. The interrupt request bits

are in interrupt request registers 1 and 2 and the interrupt enable

bits are in interrupt control registers 1 and 2. External interrupts

INT0 and INT1 can be asserted on either the falling or rising edge

as set in the edge polarity selection register. When “0” is set to this

set to the register, the interrupt is activated on the rising edge.

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