M38260ECFS datasheet(75/91 Pages) RENESAS

75 / 91 page

Rev.1.00

Sep 06, 2006

page 75 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

3.3.4 Notes on interrupts

(1)

Unused interrupts

Set the interrupt enable bit for unused interrupts to “0” (disabled).

(2)

Change of relevant register settings

When setting the followings, the interrupt request bit may be set to “1”.

•When switching external interrupt active edge

Related register: •Interrupt edge selection register (address 3A16)

•Timer X mode register (address 2716)

•Timer Y mode register (address 2816)

•When switching interrupt sources of an interrupt vector address where two or more interrupt

sources are allocated

Related register: •Interrupt source selection bit of AD control register (bit 6 of address 3416)

When not requiring for the interrupt occurrence synchronous with these setting, take the following

sequence.

Fig. 3.3.5 Sequence of changing relevant register

■ Reason

When setting the followings, the interrupt request bit of the corresponding interrupt may be set

to “1”.

•When switching external interrupt active edge

Concerned register: INT0 interrupt edge selection bit (bit 0 of Interrupt edge selection register

(address 3A16))

INT1 interrupt edge selection bit (bit 1 of Interrupt edge selection register

(address 3A16))

INT2 interrupt edge selection bit (bit 2 of Interrupt edge selection register

(address 3A16))

CNTR0 active edge switch bit (bit 6 of timer X mode register (address 2716))

CNTR1 active edge switch bit (bit 6 of timer Y mode register (address 2816))

•When switching interrupt sources of an interrupt vector address where two or more interrupt

sources are allocated.

Concerned register: Interrupt source selection bit (bit 6 of AD control register (address 3416))

Set the corresponding interrupt enable bit to “0”

(disabled) .

↓

Set the interrupt edge select bit, active edge switch

bit, or the interrupt source select bit.

↓

NOP (One or more instructions)

↓

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

↓

Set the corresponding interrupt enable bit to “1”

(enabled).

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