Rev.2.00 Mar 30, 2006 page 1 of 6

HD74HCT240

Octal Buffers/Line Drivers/Line Receivers

(with inverted 3-state outputs)

REJ03D0662–0200

(Previous ADE-205-550)

Rev.2.00

Mar 30, 2006

Description

The HD74HCT240 is an inverting buffer and has two active low enables (1

G and 2G). Each enable independently

controls 4 buffers. This device does not have schmitt trigger inputs.

Features

• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility

• High Speed Operation: t

• High Output Current: Fanout of 15 LSTTL Loads

• Wide Operating Voltage: V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: I

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HCT240P

DILP-20 pin

PRDP0020AC-B

(DP-20NEV)

P

—

HD74HCT240FPEL

SOP-20 pin (JEITA)

PRSP0020DD-B

(FP-20DAV)

FP

EL (2,000 pcs/reel)

HD74HCT240RPEL

SOP-20 pin (JEDEC)

PRSP0020DC-A

(FP-20DBV)

RP

EL (1,000 pcs/reel)

HD74HCT240TELL

TSSOP-20 pin

PTSP0020JB-A

(TTP-20DAV)

T

ELL (2,000 pcs/reel)

Note:

Please consult the sales office for the above package availability.

Function Table

Inputs

Output

G

A

Y

H

X

Z

L

H

L

L

L

H

H :

high level

L

:

low level

X :

irrelevant

Z

:

off (high-impedance) state of a 3-state output