HD74LS194A

Rev.3.00, Jul.15.2005, page 2 of 7

Function Table

Inputs

Outputs

Mode

Serial

Parallel

Clear

Clock

Left

Right

A

B

C

D

L

X

X

X

X

X

X

X

X

X

L

L

L

L

H

X

X

L

X

X

X

X

X

X

H

H

H

↑

X

X

a

b

c

d

a

b

c

d

H

L

H

↑

X

H

X

X

X

X

H

H

L

H

↑

X

L

X

X

X

X

L

H

H

L

↑

H

X

X

X

X

X

H

H

H

L

↑

L

X

X

X

X

X

L

H

L

L

X

X

X

X

X

X

X

Notes: 1. H; high level, L; low level, X; irrelevant

2.

↑; transition from low to high level

3. a to d; the level of steady-state input at inputs A, B, C, or D, respectively

established.

↑ transition of the clock.

Block Diagram

Clear

Clock

Shift

Right

Serial

Input

Shift

Left

Serial

Input

CK

S

Clear

R

CK

S

Clear

R

CK

S

Clear

R

CK

S

Clear

R

Parallel Outputs

A

Mode

Control

Inputs

BC

D

Parallel Inputs