BOARD LAYOUT

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Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

When using DIMM modules, schematics have to

be done carefully in order to avoid data busses

completely crossed on the board. This has to be

checked at the library level. In order to achive lay-

out shown in Figure 6-12, schematics have to im-

plement the crossing described on Figure 6-13.

The DQM signals must be exchanged using the

same order.

Figure 6-11. Clock routing

MCLKO

DIMMCKn input

STPCMCLKI

DIMMCKn input

DIMMCKn input

Low skewclock driver:

L

L+75mm*

20pF

* No additionnal 75mm when SDRAM directly soldered on board

Figure 6-12. Optimum data bus layout for DIMM

Figure 6-13. Schematics for optimum data bus layout for DIMM

DIMM

STPC

SDRAMI/F

D[15:00]

D[31:16]

D[47:32]

D[63:48]

MD[31:00]

MD[63:32]

MD[15:00],DQM[1:0]

MD[31:16],DQM[3:2]

MD[47:32],DQM[5:4]

MD[63:48],DQM[7:6]

D[15:00],DQM[1:0]

D[31:16],DQM[3:2]

D[47:32],DQM[5:4]

D[63:48],DQM[7:6]

DIMM

STPC