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STV82X7 Folha de dados(PDF) 44 Page - STMicroelectronics |
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STV82X7 Folha de dados(HTML) 44 Page - STMicroelectronics |
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44 / 156 page ![]() I²S Interface (In / Out) STV82x7 44/156 6.2 I²S Output A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency (fs) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required for the slave interface. Both standard and non-standard modes are available, see Figure 29. Note: The I²S input and output modes are exclusive (this means that the I2S_DATA0 can be used as input or as output). Figure 27: TQFP 80 I²S Output Block Diagram Figure 28: I²S Output Selection Audio Processing I2S_DATA0 fS Output = 32 kHz I2S_SCLK I2S_LR_CLK fS Output = 32 kHz fS Output * 64 48 kHz DSP Processing I2S_PCM_CLK fS Output * 512 LS Output C/Sub Output Srnd/HP Output SCART Output I2S_DATA0 Register 56h: Bits[7:6] |
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