AT91SAM9263 datasheet(21/1029 Pages) ATMEL

21 / 1029 page

6249B–ATARM–14-Dec-06

AT91SAM9263 Preliminary

A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the

Advanced High Performance Bus (AHB) for its master and slave interfaces with additional

features.

Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to

9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0

to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2. The bank 0 is reserved for the addressing of the

internal memories, and a second level of decoding provides 1M bytes of internal memory area.

Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus

(APB).

Other areas are unused and performing an access within them provides an abort to the master

requesting such an access.

Each master has its own bus and its own decoder, thus allowing a different memory mapping for

each master. However, in order to simplify the mappings, all the masters have a similar address

decoding.

Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are

assigned to the memory space decoded at address 0x0: one for internal boot, one for external

boot and one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 21 for

details.

A complete memory map is presented in Figure 8-1 on page 20.

8.1

Embedded Memories

•128 Kbyte ROM

– Single Cycle Access at full matrix speed

• One 80 Kbyte Fast SRAM

– Single Cycle Access at full matrix speed

– Supports ARM926EJ-S TCM interface at full processor speed

– Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen

• 16 Kbyte Fast SRAM

– Single Cycle Access at full matrix speed

8.1.1

Internal Memory Mapping

Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the

BMS state at reset.

8.1.1.1

Internal 80 Kbyte Fast SRAM

The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split

into three areas. Its memory mapping is presented in Figure 8-1 on page 20.

• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block

anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR

Table 8-1.

Internal Memory Mapping

Address

REMAP = 0

REMAP = 1

BMS = 1

BMS = 0

0x0000 0000

ROM

EBI0_NCS0

SRAM C

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