AT89C5132-ROTUL datasheet(68/182 Pages) ATMEL

68 / 182 page

4173E–USB–09/07

AT89C5132

15.1

Description

The USB device controller provides the hardware that the AT89C5132 need to interface a USB

link to data flow stored in a double port memory.

It requires a 48 MHz reference clock provided by the clock controller as detailed in Section

"Clock Controller", page 68. This clock is used to generate a 12 MHz Full Speed bit clock from

the received USB differential data flow and to transmit data according to full speed USB device

tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.

The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC

generation and checking, and the serial-parallel data conversion.

The Universal Function Interface (UFI) controls the interface between the data flow and the Dual

Port RAM, but also the interface with the C51 core itself.

Figure 15-3 shows how to connect the AT89C5132 to the USB connector. D+ and D- pins are

connected through 2 termination resistors. A pull-up resistor is implemented on D+ to inform the

host of a full speed device connection. Value of these resistors is detailed in the section “DC

Characteristics”.

Figure 15-1. USB Device Controller Block Diagram

Figure 15-2. USB Connection

15.1.1

Clock Controller

The USB controller clock is generated by division of the PLL clock. The division factor is given by

USBCD1:0 Bits in USBCLK register (see Table 70). Figure 15-3 shows the USB controller clock

USB

CLOCK

48 MHz

12 MHz

D+

D-

DPLL

SIE

UFI

USB

Buffer

To/From

C51 Core

D+

D-

VBUS

GND

D+

D-

VSS

To Power

RUSB

USB

VDD

Supply

RFS

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