AT89C51ID2-RDTIM datasheet(96/159 Pages) ATMEL

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AT89C51ID2

4289A–8051–09/03

Registers

Table 70. SSCON Register

SSCON - Synchronous Serial Control register (93h)

7654321

CR2

SSIE

STA

STO

CR1

CR0

Bit

Number

Bit

Mnemonic

Description

7CR2

Control Rate bit 2

See Table 64.

6SSIE

Synchronous Serial Interface Enable bit

Clear to disable the TWI module.

Set to enable the TWI module.

5STA

Start flag

Set to send a START condition on the bus.

4ST0

Stop flag

Set to send a STOP condition on the bus.

3SI

Synchronous Serial Interrupt flag

Set by hardware when a serial interrupt is requested.

Must be cleared by software to acknowledge interrupt.

2AA

Assert Acknowledge flag

Clear in master and slave receiver modes, to force a not acknowledge (high level

on SDA).

Clear to disable SLA or GCA recognition.

Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter

modes.

Set in master and slave receiver modes, to force an acknowledge (low level on

SDA).

This bit has no effect when in master transmitter mode.

1CR1

Control Rate bit 1

See Table 64.

0CR0

Control Rate bit 0

See Table 64.

Table 71. SSDAT (095h) - Syncrhonous Serial Data register (read/write)

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

7654321

Bit

Number

Bit

Mnemonic

Description

SD7

Address bit 7 or Data bit 7.

SD6

Address bit 6 or Data bit 6.

SD5

Address bit 5 or Data bit 5.

SD4

Address bit 4 or Data bit 4.

SD3

Address bit 3 or Data bit 3.

SD2

Address bit 2 or Data bit 2.

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