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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADN8102ACPZ-R7 Folha de dados(PDF) 5 Page - Analog Devices |
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ADN8102ACPZ-R7 Folha de dados(HTML) 5 Page - Analog Devices |
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5 / 32 page  ADN8102 Rev. A | Page 5 of 32 TIMING SPECIFICATIONS Table 2. I2C Timing Parameters Parameter Min Max Unit Description fSCL 0 400 kHz SCL clock frequency tHD:STA 0.6 N/A μs Hold time for a start condition tSU:STA 0.6 N/A μs Setup time for a repeated start condition tLOW 1.3 N/A μs Low period of the SCL clock tHIGH 0.6 N/A μs High period of the SCL clock tHD:DAT 0 N/A μs Data hold time tSU:DAT 10 N/A ns Data setup time tR 1 300 ns Rise time for both SDA and SCL tF 1 300 ns Fall time for both SDA and SCL tSU:STO 0.6 N/A μs Setup time for a stop condition tBUF 1 N/A ns Bus free time between a stop and a start condition CIO 5 7 pF Capacitance for each I/O pin S P Sr S SDA SCL tF tR tF tR tBUF tLOW tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO tHD:STA Figure 2. I2C Timing Diagram |
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