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ST7LITE09 Folha de dados(PDF) 81 Page - STMicroelectronics |
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ST7LITE09 Folha de dados(HTML) 81 Page - STMicroelectronics |
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81 / 122 page ![]() ST7LITE0, ST7SUPERLITE 81/122 13.3.2 Operating Conditions with Low Voltage Detector (LVD) TA = -40 to 125°C, unless otherwise specified Notes: 1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. 13.3.3 Auxiliary Voltage Detector (AVD) Thresholds TA = -40 to 125°C, unless otherwise specified 13.3.4 Internal RC Oscillator and PLL The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.00 3.40 2.65 4.25 3.60 2.90 4.50 3.80 3.15 V VIT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 3.65 2.90 Vhys LVD voltage threshold hysteresis VIT+(LVD)-VIT-(LVD) 200 mV VtPOR VDD rise time rate 1) 20 20000 µs/V tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150 ns IDD(LVD) LVD/AVD current consumption 200 µA Symbol Parameter Conditions Min Typ Max Unit VIT+(AVD) 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.40 3.90 3.20 4.70 4.10 3.40 5.00 4.30 3.60 V VIT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 4.10 3.40 Vhys AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 150 mV ∆V IT- Voltage drop between AVD flag set and LVD reset activation VDD fall TBD 0.45 V Symbol Parameter Conditions Min Typ Max Unit VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 V VDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP PLL Startup time 60 PLL input clock (fPLL) cycles 1 |
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