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ST7261 Folha de dados(PDF) 15 Page - STMicroelectronics |
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ST7261 Folha de dados(HTML) 15 Page - STMicroelectronics |
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15 / 80 page ![]() ST7261 15/80 Figure 14. Reset Timing Diagram Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VIT+ and VIT-. Figure 15. Reset Block Diagram Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). VDD OSCIN fCPU FFFF FFFE PC RESET tDDR tOXOV 514 CPU CLOCK CYCLES DELAY RESET RON VDD WATCHDOG RESET LVD RESET INTERNAL RESET PULSE GENERATOR 200ns Filter tw(RSTL)out + 128 fOSC delay |
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