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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ST72521 Folha de dados(PDF) 17 Page - STMicroelectronics |
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ST72521 Folha de dados(HTML) 17 Page - STMicroelectronics |
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17 / 211 page  ST72521 17/211 Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register C0h xxh 00h x000 0000b 00h 00h --- 00h Read Only R/W R/W R/W R/W R/W R/W 0058h 0059h Reserved Area (2 Bytes) 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh CAN CANISR CANICR CANCSR CANBRPR CANBTR CANPSR CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page x 00h 00h 00h 00h 23h 00h -- R/W R/W R/W R/W R/W R/W See CAN Description 0070h 0071h 0072h ADC ADCCSR ADCDRH ADCDRL Control/Status Register Data High Register Data Low Register 00h 00h 00h R/W Read Only Read Only 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh PWM ART PWMDCR3 PWMDCR2 PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2 PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register AR Timer Input Capture Control/Status Reg. AR Timer Input Capture Register 1 AR Timer Input Capture Register 1 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W Read Only Read Only 007Eh 007Fh Reserved Area (2 Bytes) Address Block Register Label Register Name Reset Status Remarks |
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