ST72141K2 datasheet(29/132 Pages) STMICROELECTRONICS

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ST72141K

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POWER SAVING MODES (Cont’d)

5.2 HALT Mode

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

ST7 HALT instruction (see Figure 21).

The MCU can exit HALT mode on reception of ei-

ther an external interrupt or a reset (see Table 2).

When exiting HALT mode by means of a RESET

or an interrupt, the oscillator is immediately turned

on and the 4096 CPU cycle delay is used to stabi-

lize the oscillator. After the start up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset vector which woke it up (see Fig-

ure 20).

When entering HALT mode, the I bit in the CC

In the HALT mode the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

Figure 20. HALT Mode timing overview

Figure 21. HALT modes flow-chart

HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

HALT INSTRUCTION

Notes:

CPU

OSCILLATOR

PERIPHERALS

I BIT

OFF

RESET

EXTERNAL*

CPU

OSCILLATOR

PERIPHERALS

OFF

INTERRUPT

HALT

FETCH RESET VECTOR

OR SERVICE INTERRUPT**

4096 clock cycles delay

CPU

OSCILLATOR

PERIPHERALS

External interrupt or internal interrupts with Exit from Halt Mode capability

** Before servicing an interrupt, the CC register is pushed on the stack.

WATCHDOG

ENABLE

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