ST63126 datasheet(43/86 Pages) STMICROELECTRONICS

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Figure 45.STD Bus (Hardware Bus Disabled) Timing Diagram

STD SPI Protocol (Shift Register)

This protocol is similar to the I

2CBUS with the ex-

ception that there is no acknowledge pulse and

there are no stop or start bits. The clock cannot be

slowed down by the external peripherals.

The I/O ports associated with the SPI should be

programmed as outputs with data high in order not

to inhibit the functionality of the hardware SPI.

SPI APPLICATION NOTES

Stop Clock Slowdown: In the ST631xx family of

devices when operating in the I

2C orSBUS modes,

there is no internal clock slowdown for the final

STOP clock. Slowdown means that if an external

peripheral requires extra time it will hold the

ST631xx SCL clock low. To be fully I

2C and SBUS

compatible in this respect, the SW should check

SERIAL PERIPHERAL INTERFACE (Continued)

that the SCL line is indeed high beforeproceeding

with the START of another I

2C or SBUS transmis-

sion. In all other cases the SCL clock slowdown

feature is operational.

SPI Standard Bus Protocol: The standard bus

protocol is selected by loading the SPI Control

2C must

be set at one and bit 1 named STD mut be reset.

When the standard bus protocol is selected bit 2 of

the SCR1 is meaningless.

This bit named STOP bit is used only in I

2CBUS or

SBUS. However take care thet THE STOP BIT

MUST BE RESET WHEN THE STANDARD PRO-

TOCOL IS USED. This bit is set to ZERO after RE-

SET.

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