ST5481

13/18

A 2.2

µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGA and GNDA.

A 1

µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD1 and

GNDD1.

A 1

µF decoupling polarized capacitor (tantal or chemical) is necessary as between VREGD2 and

GNDD2.

Note

A 10ms time constant will be used (ex: 470 nF, 20

Ω) to generate an adequate pulse on NRESET pin.

Table 6 : Digital Pins (except GPIO4 to GPIO7,XTALin, XTALout, RPSM, NRESET)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Low level input voltage

V

High level input voltage

V

Low level input voltage (ILoad = 2mA)

0.4

V

High Level Output Voltage (Iload = -2mA)

V

Input Leakage Current

1

uA

Low level input Current (0<Vol<Volmax)

-2

mA

High Level Output Current (Vohmin<Vof<VregD1)

2

mA

Schmitt Trigger Hysteresis

0.8

V

Input Capacitance

3

pF

Table 7 : GPIO4, GPIO5, GPIO6, GPIO7.

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Low level input voltage

V

High level input voltage

V

Low level input voltage (Iload = 2mA)

0.4

V

High Level Output Voltage (Iload = -2mA)

V

Input Leakage Current

1

uA

Low level input Current (0<Vol<Volmax)

-4

mA

High Level Output Current (Vohmin<Vof<VregD1)

4

mA

Schmitt Trigger Hysteresis

0.8

V

Input Capacitance

3

pF

Table 8 : RPSM, NRESET.(5 volt inputs compatible)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Low level input voltage

V

High level input voltage

V

Schmitt Trigger Hysteresis

1

1.3

V