ICS87993I datasheet(7/16 Pages) ICST

Nome de Peças	ICS87993I

Descrição Electrónicos	1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

PDF	16 Pages

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Fabricante Electrônico	ICST [Integrated Circuit Systems]

Página de início	http://www.icst.com

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87993AYI

www.icst.com/products/hiperclocks.html

REV. B May 21, 2003

Integrated

Circuit

Systems, Inc.

ICS87993I

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Figure 3 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

CC = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

0.1u

Single Ended Clock Input

CLKx

nCLKx

VCC

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