ST10F167 datasheet(26/69 Pages) STMICROELECTRONICS

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ST10F167

GENERAL PURPOSE TIMER (GPT) UNIT

The GPT unit is a flexible multifunctional timer/

counter structure. It may be used for many differ-

ent time-related tasks such as: event timing and

counting, pulse width and duty cycle measure-

ments, pulse generation or pulse multiplication.

The GPT unit incorporates five 16-bit timers which

are organized in two separate modules, GPT1 and

GPT2. Each timer, in each module may operate in-

dependently in a number of different modes, or

may be concatenated with another timer of the

same module.

Each of the three timers T2, T3, T4 of module

GPT1 can be configured individually for one of

three basic modes of operation: Timer, Gated Tim-

er, and Counter Mode. In Timer Mode, the input

clock for a timer is derived from the CPU clock, di-

vided by a programmable prescaler. Counter

Mode allows a timer to be clocked in reference to

external events. Pulse width or duty cycle meas-

urement is supported in Gated Timer Mode where

the operation of a timer is controlled by the ‘gate’

level on an external input pin. Each timer has one

associated port pin (TxIN) which serves as gate or

clock input. The maximum resolution of the timers

in module GPT1 is 400ns (@ 20MHz CPU clock).

The count direction (up/down) for each timer is

programmable by software or may be altered dy-

namically by an external signal on a port pin (Tx-

EUD) to facilitate, for example, position tracking.

Timers T3 and T4 have output toggle latches (Tx-

OTL) which change their state on each timer over-

flow/underflow. The state of these latches may be

output on port pins (TxOUT) for time-out monitor-

ing by external hardware components, or may be

used internally to clock timers T2 and T4 for meas-

uring long time periods with high resolution.

In addition to their basic operating modes, timers

T2 and T4 may be configured as reload or capture

registers for timer T3. When used as capture or re-

load registers, timers T2 and T4 are stopped. The

contents of timer T3 are captured into T2 or T4 in

response to a signal at their associated input pins

(TxIN). Timer T3 is reloaded with the contents of

T2 or T4, triggered, either by an external signal, or

by a selectable state transition of its toggle latch

T3OTL. When both T2 and T4 are configured to al-

ternately reload T3 on opposite state transitions of

T3OTL with the low and high times of a PWM sig-

nal, this signal can be constantly generated with-

out software intervention.

With its maximum resolution of 160 ns (@

20MHz), the GPT2 module provides precise event

control and time measurement. It includes two tim-

ers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an in-

put clock which is derived from the CPU clock via a

programmable prescaler or with external signals.

The count direction (up/down) for each timer is

programmable by software or may additionally be

altered dynamically by an external signal on a port

pin (TxEUD). Concatenation of the timers is sup-

ported via the output toggle latch (T6OTL) of timer

T6, which changes its state on each timer over-

flow/underflow.

The state of this latch may be used to clock timer

T5, or it may be output on a port pin (T6OUT). The

overflows/underflows of timer T6 can additionally

be used to clock the CAPCOM timers T0 or T1,

and to cause a reload from the CAPREL register.

The CAPREL register may capture the contents of

timer T5 based on an external signal transition on

the corresponding port pin (CAPIN), and timer T5

may optionally be cleared after the capture proce-

dure. This allows absolute time differences to be

measured or pulse multiplication to be performed

without software overhead.

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