74LVC161

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 6 — 30 September 2013

13 of 22

NXP Semiconductors

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 12. Set-up and hold times for the input (Dn) and parallel enable input (PE)

mna914

GND

GND

GND

th

th

tsu

tsu

tsu

th

th

tsu

VM

VM

VM

VI

VI

CP input

PE input

Dn input

VI

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 13. CEP and CET set-up and hold times

mna915

th

tsu

th

tsu

GND

VI

VM

VM

GND

VI

CP input

CEP, CET input

Table 8.

Measurement points

Supply voltage

Input

Output

VCC

VI

VM

VM

1.2 V

VCC

0.5

 V

CC

0.5

 V

CC

1.65 V to 1.95 V

VCC

0.5

 V

CC

0.5

 V

CC

2.3 V to 2.7 V

VCC

0.5

 V

CC

0.5

 V

CC

2.7 V

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

2.7 V

1.5 V

1.5 V