PSD934210MIT datasheet(80/89 Pages) STMICROELECTRONICS

80 / 89 page

PSD834F2V

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Table 52. Reset (Reset) Timing

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.

Table 53. VSTBYON Timing

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.

Table 54. ISC Timing

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time 1

300

tNLNH–PO

Power On Reset Active Low Time

tNLNH–A

Warm Reset 2

µs

tOPR

RESET High to Operational Device

300

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

µs

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

µs

Symbol

Parameter

Conditions

-10

-15

-20

Unit

Min

Max

Min

Max

Min

Max

tISCCF

Clock (TCK, PC1) Frequency (except for

PLD)

(Note 1)

MHz

tISCCH

Clock (TCK, PC1) High Time (except for

PLD)

(Note 1)

tISCCL

Clock (TCK, PC1) Low Time (except for

PLD)

(Note 1)

tISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note 2)

222

MHz

tISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note 2)

240

tISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note 2)

240

tISCPSU

ISC Port Set Up Time

tISCPH

ISC Port Hold Up Time

tISCPCO

ISC Port Clock to Output

tISCPZV

ISC Port High-Impedance to Valid Output

tISCPVZ

ISC Port Valid Output to

High-Impedance

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