PSD813F1 datasheet(35/120 Pages) STMICROELECTRONICS

Nome de Peças	PSD813F1

Descrição Electrónicos	Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PDF	120 Pages

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Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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Preliminary

PSD813F1-A

The

PSD813F1

Functional

Blocks

(cont.)

FLASH

DPLD

EEPROM

SRAM

RS0

EES0-3

FS0-7

PSEN

Figure 8. 8031 Memory Modes – Separate Space Mode

FLASH

DPLD

EEPROM

SRAM

RS0

EES0-3

FS0-7

VM REG BIT 2

PSEN

VM REG BIT 0

VM REG BIT 1

VM REG BIT 3

VM REG BIT 4

Figure 9. 80C31 Memory Mode – Combined Space Mode

9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces

9.1.3.2.1 Separate Space Modes

Code memory space is separated from data memory space. For example, the PSEN

signal is used to access the program code from the Flash Memory, while the RD signal is

used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires

the VM register to be set to 0Ch.

9.1.3.2.2 . Combined Space Modes

The program and data memory spaces are combined into one space that allows the main

Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example,

to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM

9.1.3.3 80C31 Memory Map Example

See Application Notes 57 and 64 for examples.

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