9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

16

9DB433

MAY 25, 2018

Revision History

Issue Date Description

Page #

6/30/2010 Released to final

5/9/2011

1. Update pin 1 pin-name and pin description from VDD to VDDR. This highlights that optimal

performance is obtained by treating VDDR as in analog pin. This is a document update only,

there is no silicon change.

Various

3/13/2012

1. Added additional line to PLL Bandwidth "-3dB point in High BW Mode" conditions for

industrial mode (min1.5, typ 2.7, max 4.1 MHz)

2. Added additional line to Skew, Input to Output "Bypass Mode" conditions for industrial

mode (min 2500, max 4900 ps)

6

7/5/2012

1. Changed references of PCIe Gen3 to PCIe Gen1,2,3

1

7/12/2012 1. Added missing typical values to DS.

Various

9/18/2012

Updated Byte 2, bits 1, 2, 5 and 6 per char review. Outputs can be programmed with Byte 2

to be Stoppable or Free-Run with DIF_Stop pin, not the OE pins.

Various

9/30/2013 Corrected typo in ordering information for 28-SSOP I-temp device.

15

8/14/2015

1. Corrected default value of Byte 2 to 00hex. Added note referring to 9DB434 if FFhex is

the desired default.

11

6/7/2016

1. Corrected Idd values for 9DB433.

2. Updated typical values in electrical tables.

3. Updated clock input electrical table to latest format.

4. Updated SMbus operating frequency to 440KHz.

5. Corrected typo in Byte 0, bit 6 defaults to 0.

Various

5/25/2018 1. Updated the minimum input slew rate from 1 V/ns to 0.6V/ns.

6