RZSLASHT2ME datasheet(9/116 Pages) RENESAS

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Table 1.11

Safety

Feature

Functional description

Memory protection unit (MPU)

● Cortex-R52 MPU

Two stages MPUs (EL2 and EL1)

24 regions each MPU

● Master MPU

Memory protection for masters except Cortex-R52 (DMAC, USB, Ethernet MAC, CoreSight)

Protects important registers from being overwritten for in case a program runs out of control.

CRC calculator (CRC)

● 2 channels

● CRC code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units

● Select any of four generating polynomials:

– X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

(32-Ethernet)

– X32 + X28 + X27 + X26 + X25 + X23 + X22 + X20 + X19 + X18 + X14 + X13 + X11 + X10 +

X9 + X8 + X6 + 1 (CRC-32C)

– X16 + X15 + X2 + 1 (CRC-16)

– X16 + X12 + X5 + 1 (CRC-CCITT)

– X8 + X2 + X + 1 (CRC-8)

Clock monitor circuit (CLMA)

● Monitors the abnormal output clock frequency from the input clock (main clock oscillator),

PLL circuit, or low-speed on-chip oscillator.

● Input clock oscillation stop detection: Available

Data operation circuit (DOC)

The function to compare, add, or subtract 16-bit data

Isolated peripherals

● Safety dedicated peripherals are available:

– GPT: 4 ch

– SCI: 1 ch

– IIC: 1 ch

– SPI: 1 ch

– CRC: 1 unit

– RTC: 1 unit

– GPIO: Sharable with normal GPIO

– On-chip system SRAM with ECC

● They are mapped independently from normal peripherals so that access protection can be

done by EL2 MPU.

Table 1.12

Security

Feature

Functional description

Security

● Secure boot

● JTAG authentication

● SCI/USB boot disable

● Cryptographic accelerators

– Symmetric Cipher: AES 128/192/256 bits with CBC/ECB/CTR/GCM/XTS

– Asymmetric Cipher: ECC 256 bits, RSA 1024/2048/3072 bits, RSAES-OAEP

– Hash: SHA-1, SHA-2

– Message authentication: HMAC, CMAC, GMAC

– Signature algorithms: ECDSA with NIST P-256, RSASSA-PSS, RSASSA-PKCS1

● TRNG

Table 1.13

Debug

Feature

Functional description

Debugging interface

● CoreSight architecture designed by Arm

● Debugging function by the JTAG/SWD interface, and trace function by the trace port

interface

Table 1.14

Others (1 of 2)

Feature

Functional description

Power supply voltage

VDD = 1.1 V (Core)

VCC18 = 1.8 V (PLL, USB, ADC, TSU)

VCC33 = 3.3 V (I/O, USB)

VCC1833 = 1.8 V (RGMII, xSPI) or 3.3 V (RMII/MII, xSPI*1)

Operating temperature

Tj = −40 to +125°C

RZ/T2ME Datasheet

1. Overview

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

Page 9 of 116

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