R5F5671CDDFM datasheet(91/179 Pages) RENESAS

91 / 179 page

R01DS0373EJ0120 Rev.1.20

Page 91 of 179

Sep 30, 2024

RX671 Group

2. Electrical Characteristics

2.4.1

Reset Timing

Figure 2.1

Reset Input Timing at Power-On

Figure 2.2

Reset Input Timing

Table 2.14

Reset Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

RES# pulse

width

Power-on

tRESWP

—

Figure 2.1

Deep software standby mode

tRESWD

0.6

—

Figure 2.2

Software standby mode, low-speed operating

mode 2

tRESWS

0.3

—

Programming or erasure of the code flash

memory, or programming, erasure or blank

checking of the data flash memory

tRESWF

200

—

µs

Other than above

tRESW

200

—

µs

Waiting time after release from the RES# pin reset

tRESWT

—

tLcyc

Figure 2.1

Internal reset time

(independent watchdog timer reset, watchdog timer reset,

software reset)

tRESW2

100

—

108

tLcyc

VCC

RES#

Internal reset signal

(Low is valid)

tRESWP

tRESWT

RES#

Internal reset signal

(Low is valid)

tRESWD, tRESWS, tRESWF, tRESW

tRESWT

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