R5F5671CDDFB datasheet(6/179 Pages) RENESAS

6 / 179 page

RX671 Group

1. Overview

R01DS0373EJ0120 Rev.1.20

Page 6 of 179

Sep 30, 2024

Timers

Compare match timer

(CMT)

 (16 bits × 2 channels) × 2 units

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Event linking by the ELC

Compare match timer W

(CMTW)

 (32 bits × 1 channel) × 2 units

 Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

 Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

 Event linking by the ELC

Watchdog timer (WDTA)

 14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Multifunction timer pulse

unit (MTU3a)

 9 channels (16 bits × 8 channels, 32 bits × 1 channel)

 Maximum of 28 pulse-input/output and 3 pulse-input possible

 Select from among 14 counter-input clock signals for each channel (PCLKA/1, PCLKA/

2, PCLKA/4, PCLKA/8, PCLKA/16, PCLK/A32, PCLKA/64, PCLKA/256, PCLKA/1024,

MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)

14 of the signals are available for channel 0, 11 are available for channels 1, 3, 4, 6 to 8,

12 are available for channel 2, and 10 are available for channel 5.

 Input capture function

 39 output compare/input capture registers

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffered operation

 Support for cascade-connected operation

 43 interrupt sources

 Automatic transfer of register data

 Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

Outputs non-overlapping waveforms for controlling 3-phase inverters

Automatic specification of dead times

PWM duty cycle: Selectable as any value from 0% to 100%

Delay can be applied to requests for A/D conversion.

Non-generation of interrupt requests at peak or trough values of counters can be

selected.

Double buffer configuration

 Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired duty

cycles.

 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)

 Counter functionality for dead-time compensation

 Generation of triggers for A/D converter conversion

 A/D converter start triggers can be skipped

 Digital filter function for signals on the input capture and external counter clock pins

 PPG output trigger can be generated

 Event linking by the ELC

Port output enable 3

(POE3a)

 Control of the high-impedance state of the MTU waveform output pins

 5 pins for input from signal sources: POE0#, POE4#, POE8#, POE10#, POE11#

 Initiation on detection of short-circuited outputs (detection of simultaneous PWM output

to the active level)

 Initiation by oscillation-stoppage detection or software

 Additional programming of output control target pins is enabled

Table 1.1

Outline of Specifications (5/10)

Classification

Module/Function

Description

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