R5F564MLGDLC datasheet(76/162 Pages) RENESAS

76 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 76 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.2

Clock Timing

Figure 2.3

BCLK Pin and SDCLK Pin Output Timing

Table 2.13

BCLK Pin Output, SDCLK Pin Output Clock Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

BCLK pin output cycle time

Packages with 177 to

144 pins

tBcyc

16.6

—

Figure 2.3

Packages with 100

pins or less

33.2

—

BCLK pin output high pulse width

tCH

3.3

—

BCLK pin output low pulse width

tCL

3.3

—

BCLK pin output rising time

tCr

——

BCLK pin output falling time

tCf

——

SDCLK pin output cycle time

Packages with 177 to

144 pins

tSDcyc

16.6

—

SDCLK pin output high pulse width

tCH

3.3

—

SDCLK pin output low pulse width

tCL

3.3

—

SDCLK pin output rising time

tCr

——

SDCLK pin output falling time

tCf

——

tCf

tCH

tBcyc, tSDcyc

tCr

tCL

BCLK pin output, SDCLK pin output

Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF

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