R7KA8D2AFDCAC datasheet(64/292 Pages) RENESAS

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Table 2.14

Current of high-speed mode, maximum data processing (MVE operation), CPU0 active, CPU1 Deep

Sleep, peripheral clock ON (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1*2

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VSCR_1

ICC_DCDC*4

136

322

—

VCC_DCDC = 3.3 V

CPU1 = Deep Sleep

IDD*3

349

827

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*4

113

—

341

IDD*3

290

—

877

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VSCR_2

ICC_DCDC*4

265

306

IDD*3

216

693

801

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows.

IDD Typ. = 0.25 × fCPUCLK0 + 0.35 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.27 × fCPUCLK0 + 0.46 × fICLK + 487 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.27 × fCPUCLK0 + 0.46 × fICLK + 565 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.27 × fCPUCLK0 + 0.61 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.27 × fCPUCLK0 + 0.61 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. Same frequency condition is applied as in the maximum condition.

Table 2.15

Current of high-speed mode, maximum data processing (MVE operation), CPU0 active, CPU1 Deep

Sleep, peripheral clock ON (External VDD mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

Supply

current

*1*2

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VCL = voltage

range 1

IDD*3

349

827

—

CPU1 = Deep Sleep

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD*3

290

—

877

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VCL = voltage

range 2

IDD*3

216

693

801

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows.

IDD Typ. = 0.25 × fCPUCLK0 + 0.35 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 95℃) = 0.27 × fCPUCLK0 + 0.46 × fICLK + 487 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 1, 105℃) = 0.27 × fCPUCLK0 + 0.46 × fICLK + 565 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 95℃) = 0.27 × fCPUCLK0 + 0.61 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VCL = voltage range 2, 105℃) = 0.27 × fCPUCLK0 + 0.61 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 64 of 292

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