AS7343L datasheet(41/53 Pages) AMSOSRAM

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AS7343L

Datasheet

• PUBLIC

DS001038

• v2-00 • 2022-Aug-12

│ 40

Addr: 0xD6

CFG20

Bit

Bit Name

Default

Access

Bit Description

6:5

auto_smux

Automatic Channel Read-Out.

0: 6 Channel

FZ, FY, FXL, NIR, 2xVIS, Clear

1: Reserved

2: Automatic 12 channel

Cycle 1: FZ, FY, FXL, NIR, 2xVIS, Clear

Cycle 2: F2, F3, F4, F6, 2xVIS, Clear

3: Automatic 18 channel

Cycle 1: FZ, FY, FXL, NIR, 2xVIS, Clear

Cycle 2: F2, F3, F4, F6, 2xVIS, Clear

Cycle 3: F1, F5, F7, F8, 2xVIS, Clear

Note: The

bit “auto_smux” should only be changed

before a measurement is started.

Once a measurement is started the device is

automatically processing the channels as per

definition above and storing the measurement

results in the eighteen data registers.

2xVIS: Per

default the “Top Left” and “Bot Right”

VIS/CLEAR PD is read-out

4:0

Reserved

PERS Register (Address 0xCF)

Figure 53:

PERS Register

Addr: 0xCF

PERS

Bit

Bit Name

Default

Access

Bit Description

7:4

Reserved

3:0

APERS

Spectral Interrupt Persistence.

Defines a filter for the number of consecutive

occurrences that spectral data must remain outside

the threshold range between SP_TH_L and

SP_TH_H before an interrupt is generated. The

spectral data channel used for the persistence filter

is set by SP_TH_CHANNEL. Any sample that is

inside the threshold range resets the counter to 0.

VALUE

CHANNEL

Every spectral cycle generates an

interrupt

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