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AS7343

Datasheet

• PUBLIC

DS001046

• v6-00 • 2023-Jun-07

│ 44

CFG20 Register (Address 0xD6)

Figure 57:

CFG20 Register

Addr: 0xD6

CFG20

Bit

Bit Name

Default

Access

Bit Description

FD_FIFO_8b

Enable 8-bit FIFO Mode for Flicker Detection.

0: Disabled

1: Enabled

Note: FD_TIME must be smaller than 256, else

flicker data might be larger than 8 bit. In that case

flicker data gets saturated to 0xFF.

6:5

auto_smux

Automatic Channel Read-Out

0: 6 Channel

FZ, FY, FXL, NIR, 2xVIS, FD

1: Reserved;

2: Automatic 12 channel

Cycle 1: FZ, FY, FXL, NIR, 2xVIS, FD

Cycle 2: F2, F3, F4, F6, 2xVIS, FD

3: Automatic 18 channel

Cycle 1: FZ, FY, FXL, NIR, 2xVIS, FD

Cycle 2: F2, F3, F4, F6, 2xVIS, FD

Cycle 3: F1, F7, F8, F5, 2xVIS, FD

Note: T

he bit “auto_smux” should only be changed

before a measurement is started.

Once a measurement is started, the device is

automatically processing the channels as per

definition above and storing the measurement

results in the eighteen data registers.

2xVIS: P

er default the “Top Left” and “Both Right”

VIS/CLEAR PD is read-out.

4:0

Reserved

PERS Register (Address 0xCF)

Figure 58:

PERS Register

Addr: 0xCF

PERS

Bit

Bit Name

Default

Access

Bit Description

7:4

Reserved

3:0

APERS

Spectral Interrupt Persistence.

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