AS7341 datasheet(32/69 Pages) AMSOSRAM

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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 31

INTENAB Register (Address 0xF9)

Figure 38:

INTENAB Register

Addr: 0xF9

INTENAB

Bit

Bit Name

Default

Access

Bit Description

ASIEN

Spectral and Flicker Detect Saturation Interrupt

Enable.

When asserted permits saturation interrupts to be

generated.

6:4

reserved

SP_IEN

Spectral Interrupt Enable.

When asserted permits interrupts to be generated,

subject to the spectral thresholds and persistence

filter. Bit is mirrored in the ENABLE register.

F_IEN

FIFO Buffer Interrupt Enable.

When asserted permits interrupt to be generated

when FIFO_LVL exceeds the FIFO threshold

condition.

reserved

SIEN

System Interrupt Enable.

When asserted permits system interrupts to be

generated. Indicates that flicker detection status has

changed or SMUX operation has finished.

CONTROL Register (Address 0xFA)

Figure 39:

CONTROL Register

Addr: 0xFA

CONTROL

Bit

Bit Name

Default

Access

Bit Description

7:3

reserved

SP_MAN_AZ

Spectral Engine Manual Autozero.

Starts a manual autozero of the spectral engines.

Set SP_EN = 0 before starting a manual autozero for

it to work.

FIFO_CLR

FIFO Buffer Clear.

Clears all FIFO data, FINT, FIFO_OV, and

FIFO_LVL.

CLEAR_SAI_ACT

Clear Sleep-After-Interrupt Active.

Clears SAI_ACTIVE, ends sleep, and restarts device

operation.

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